The present invention relates to semiconductor devices, and more specifically, to combined reactive gas species for high-mobility channel passivation.
A metal-oxide-semiconductor field-effect transistor (MOSFET) is a transistor used for amplifying or switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or glass, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”). A fin type field effect transistor (FET) is a type of MOSFET. FinFET devices include an arrangement of fins disposed on a substrate. The fins are formed from a semiconductor material. A gate stack is arranged over the fins and defines a channel region of the fins, while regions of the fins extending outwardly from the channel region define active source and drain regions of the device. Various state-of-the-art techniques may be used for forming the fin.
A particular obstacle facing the development of metal-oxide semiconductor field-effect transistors with, for example, InGaAs channels is the high density of traps (Dit) at the gate dielectric/III-V semiconductor interface. Typical capacitance-voltage (CV) curves of unpinned metal-oxide-semiconductor capacitors (MOSCAPs) on n-InGaAs show a frequency-dependent “hump” at negative biases, characteristic of midgap Dit response. Studies have focused on Al2O3 or HfO2/Al2O3 bilayers, as Al2O3 is believed to allow for lower Dit than HfO2. Also, to reduce the Dit, various passivation approaches have been examined in the literature, including treatment with sulfur containing agents, As-decapping, hydrogen plasma, and hydrogenation/nitridization.
Furthermore, obtaining a pristine and/or passivated semiconductor surface without damaging the bulk of the film is critical to gate stack and contact formation in order to improve transfer characteristics (mobility, sub-threshold slope, etc.) and reduce resistivity, respectively. This is particularly challenging for high-mobility semiconductors (such as InGaAs and SiGe) for which a low quality native oxide readily forms after air exposure so that wet chemistry is not sufficient to condition the substrate appropriately. This also adds a queue-time dependence between wet chemical treatment and dielectric gate or metal contact deposition so that the integration is rendered non-practical in a manufacturing setting. On III-V substrates, proposed solutions for bare surfaces are limited due to, for example, the small process compatibility window (e.g., temperature up to 400° C.). Sulfur-containing chemistry only slows oxide regrowth and yields downstream tool contamination.